3D EDA Research Group is a Romanian Organization established to develop the next generation of 3D EDA tools. The purpose of the research is to develop a tool capable of optimized generation of 3D circuits, while extensively using existing 2D tools. The tool takes several possible approaches at partitioning, including: partitioning memories and logic to separate layers; optimizing average interconnection length; partitioning cells to different technological processes for different active layers. The Research Group: Top researchers in monolithic 3D EDA with international recognition in industry. Engineers with strong background in EDA tool development. International Collaboration between private and academic environment.
Research Engineers: Strong research experience in design methodologies and CAD for emerging nanotechnologies. Experience in development and usage of commercial EDA tools for front-end/back-end design with 45nm to 16nm technologies both under commercial and predictive model. Knowledge on design techniques bridging process, design, and CAD for early performance evaluation of emerging nanotechnologies. Achievements: Three patents and more than 20 publications in reputed international proceedings and journals.
Analytic geometry algorithms implementation and software development: "nanoDRC" - is a Design Rule aware integrated circuit layout design environment. The tool analyzes the IC layout block’s database during construction and automatically advises/corrects design rule violations, maintaining the process design rule correctness, provides a real-time DRC-Aware design environment within Cadence’s layout editor. (Virtuoso LE, XL, GXL), provides full nanometer support, including deep nanometer ranges (65nm, 45nm, 32nm). "nanoLVS™" - a nanometer range EDA tool that corrects connectivity mismatches in an integrated circuit layout block. The tool reads the IC layout blocks and its netlist and automatically corrects connectivity mismatches, maintaining the process design rule correctness. In addition, nanoLVS™ provides a real-time LVS correction environment within layout editors. The project was developed for Micrologic Design Automation - EDA Tools Interactive Tools for Design and Verification of Nanometer ICs.
Furthermore the strong relationship between the academic and private environment led to a public funded project proposal of $800,000. Based on the research for the next generation of 3D EDA tools a consortium of three partners was established. Leading academic personnel in collaboration with top researches form the private environment applied for governmental funds to carry out the research in developing EDA tools targeting at monolithic 3D technology. MonolithIC 3D Inc. plays a key role in the development of the project as a private collaborator with its IP portfolio with over 50 patents in the semiconductor field. The company is a world leader for monolithic 3D technology gathering top researches with more than 20 years of experience in the semiconductor industry. The members of the board of advisory are leading scientists in the field of monolithic 3D ICs. They are Sung Kyu Lim, Associate Professor at the School of Electrical and Computer Engineering at Georgia Institute of Technology and Bipin Rajendran, Assistant Professor in the Department of Electrical Engineering at I.I.T. Bombay. The board provides valuable perspective and counsel to the executive team at MonolithIC 3D in the areas of business development, technology issues and future road map. Dr. Sung Kyu Lim and his Georgia Tech team are leading the research of monolithic 3D physical design and analysis tools and will add the EDA aspect to our innovation efforts.